IBM Personal Computer PC 300PL User Manual
Technical Information Manual  
PC 300PL Personal Computer Types 6584 and 6594  
 
Contents  
Preface  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii  
Related publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii  
Terminology usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii  
Chapter 1. System overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Major features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Other features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Network support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
1
1
2
2
2
3
Wake on LAN  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Wake on Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Chapter 2. System board features  
Pentium III microprocessor with MMX technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Features  
L2 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Chip set control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
System memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
PCI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
IDE bus master interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4
4
4
4
4
5
6
6
6
7
7
9
9
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
USB interface  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Low pin count bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Video subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Monitor support  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Video memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Audio subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Super input/output controller  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Diskette drive interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Parallel port  
Keyboard and mouse ports  
Network connection  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Real-time clock and CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Expansion adapters  
Physical layout  
System board, Types 6584 and 6594  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Riser card layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Recovery jumper  
Cable connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Connector panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Chapter 3. Physical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
PC 300PL — desktop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
PC 300PL — tower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Cabling requirements for Wake on LAN adapters  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Chapter 4. Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Power input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Power output  
Component outputs  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Copyright IBM Corp. September 1999  
 
iii  
Output protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Connector description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Chapter 5. System software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Plug and Play . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
POST  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Configuration/Setup Utility program  
Advanced Power Management (APM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Advanced Configuration and Power Interface (ACPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Flash update utility program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Diagnostic program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Chapter 6. System compatibility  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Hardware compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Hard disk drives and controller  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Software compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Software interrupts  
Machine-sensitive programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Appendix A. Connector pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Monitor connector  
Memory connectors  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
PCI connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
ISA connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
IDE connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Diskette drive connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Power supply connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Wake on LAN connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Alert on LAN connectors  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Tamper detection switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Radio frequency ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
SCSI high frequency LED connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
CD audio connector  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
USB port connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Mouse and keyboard port connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Serial port connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Parallel port connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Appendix B. System address maps  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
System memory map  
Input/output address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
DMA I/O address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
PCI configuration space map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Appendix C. IRQ and DMA channel assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Appendix D. Error codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
POST error codes  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Beep codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Appendix E. Notices and trademarks  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
iv Technical Information Manual  
 
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Contents  
v
 
Figures  
1. Memory configurations for 133 MHz FSB  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5
8
9
2. Video subsystem resources  
3. Supported VGA video modes  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4. Serial port assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
5. Parallel port assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
6. Recovery jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
7. Power-input requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
8. Power-output (145 watts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
9. Power output (200 watts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
10. System board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
11. Keyboard port  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
12. PCI-bus adapters (per slot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
. . . . . . . . . . . . . . . . . . . . . 25  
13. USB port  
14. Internal DASD  
15. Monitor port connector pin assignments—SVGA  
16. Monitor port connector pin assignments—DVI main pin field  
17. Monitor port connector pin assignments—DVI MicroCross section . . . . . . . . . . . . . . . . . . 26  
18. System memory connector pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
19. PCI connector pin assignments  
20. ISA connector pin assignments  
21. IDE connector pin assignments  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
22. Diskette drive connector pin assignments  
23. Power supply connector pin assignments  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
24. Wake on LAN connector pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
25. Alert on LAN connector pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
26. Tamper switch pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
27. Radio frequency identification (RFID) pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . 32  
28. SCSI high frequency LED connector pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . 33  
29. CD audio connector pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
30. USB port connector pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
31. Mouse port connector pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
32. Keyboard port connector pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
33. Serial port connector pin assignments  
34. Parallel port connector pin assignments  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
35. System memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
36. I/O address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
37. DMA I/O address map  
38. IRQ channel assignments  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
39. DMA channel assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
vi  
Copyright IBM Corp. September 1999  
 
Preface  
This Technical Information Manual provides information for the IBMPC 300Types 6584 and 6594. It is  
intended for developers who want to provide hardware and software products to operate with these IBM  
computers and provides an in-depth view of how these IBM computers work. Users of this publication  
should have an understanding of computer architecture and programming concepts.  
Related publications  
In addition to this manual, the following IBM publications provide information related to the operation of the  
IBM PC 300PL Personal Computer:  
Ÿ PC 300PL User Guide  
This publication contains information about configuring, operating, and maintaining the PC 300PL  
Personal Computer, as well as installing new options in the PC 300PL Personal Computer. Also  
included are warranty information, instructions for diagnosing and solving problems, and information on  
how to obtain help and service.  
Ÿ Understanding Your Personal Computer  
This online document includes general information about using computers and detailed information  
about the features of the PC 300PL Personal Computer.  
Ÿ About Your Software  
This publication (provided only with computers that have IBM-preinstalled software) contains  
information about the preinstalled software package.  
Ÿ Hardware Maintenance Manual  
This publication contains information for trained service technicians. It is available at  
http://www.ibm.com/pc/us/cdt/hmm.html on the World Wide Web, and it can also be ordered from IBM.  
To purchase a copy, see the "Getting Help, Service, and Information" section in PC 300PL User  
Guide.  
Ÿ Compatibility Report  
This publication contains information about compatible hardware and software for the PC 300PL  
Personal Computer. It is available at http://www.ibm.com/pc/us/cdt on the World Wide Web.  
Ÿ Network Administrator's Guide  
This publication contains information for network administrators who configure and service local area  
networks (LANs). Look for this publication at http://www.ibm.com/pc/us/cdt on the World Wide Web.  
Terminology usage  
Attention: The term reserved describes certain signals, bits, and registers that should not be changed.  
Use of reserved areas can cause compatibility problems, loss of data, or permanent damage to the  
hardware. When the contents of a register are changed, the state of the reserved bits must be preserved.  
When possible, read the register first and change only the bits that must be changed.  
In this manual, some signals are represented in a small, all-capital-letter format (-ACK). A minus sign in  
front of the signal indicates that the signal is active low. No sign in front of the signal indicates that the  
signal is active high.  
The use of the term hex indicates a hexadecimal number.  
Copyright IBM Corp. September 1999  
 
vii  
When numerical modifiers such as K, M, and G are used, they typically indicate powers of 2, not powers  
of 10. For example, 1 KB equals 1024 bytes (2 10), 1 MB equals 1048576 bytes (2 20), and 1 GB equals  
1073741824 bytes (230).  
When expressing storage capacity, MB equals 1000 KB (1024000). The value is determined by counting  
the number of sectors and assuming that every two sectors equals 1 KB.  
Note: Depending on the operating system and other system requirements, the storage capacity available  
to the user might vary.  
viii Technical Information Manual  
 
Chapter 1. System overview  
Chapter 1. System overview  
PC 300PL Types 6584 and 6594 are computer systems designed to provide state-of-the-art computing  
power with room for future growth.  
Major features  
The major features are:  
Ÿ An IntelPentiumIII microprocessor with MMXtechnology, streaming single instruction multiple  
data (SIMD) extensions, and 256 KB L2 cache  
Ÿ Up to 1 GB of system memory  
Ÿ Integrated IDE bus master controller, Ultra DMA/66 capable  
Ÿ EIDE hard disk drive  
Ÿ System management  
– Wake on LANsupport  
– Desktop Management Interface (DMI) BIOS and DMI software  
– Integrated network protocols  
– Enablement for remote administration  
– Wake on Ring support  
Ÿ IDE CD-ROM1 drive, standard on some models  
Ÿ Asset security  
– Security settings provided by the Configuration/Setup Utility program  
- Power-on and administrator password protection  
- Startup sequence control  
- Hard disk drive and diskette drive access control  
- I/O port control  
– Cover key lock  
– U-bolt and security cabling (optional)  
– Operating system security  
– Diskette write-protection  
– Alert on LANsupport  
– Tamper-detection switch on the chassis  
Ÿ Accelerated graphics port (AGP) adapter  
Ÿ Integrated 16-bit stereo audio controller and built-in high-quality speaker in some models (supports  
SoundBlaster, Adlib, and MicrosoftWindowsSound System applications)  
Ÿ Networking  
– IBM 10/100 megabits-per-second (Mbps) PCI Ethernet adapter with Wake on LAN support in  
some models  
– IBM PCI token ring adapter with Wake on LAN support (optional)  
1
Variable read rate. Actual playback speed will vary and is often less than the maximum possible.  
Copyright IBM Corp. September 1999  
1
 
Chapter 1. System overview  
Ÿ Expansion  
Desktop  
– Four drive bays  
– Four PCI expansion slots  
Tower  
– Six drive bays  
– Six PCI expansion slots  
Ÿ PCI I/O bus compatibility  
Ÿ EnergyStar compliance (some models only)  
Ÿ 3.5-inch, 1.44 MB diskette drive  
Ÿ Input/output features  
– One 25-pin, parallel port with Extended Capabilities Port (ECP)/Extended Parallel Port (EPP)  
support  
– Two 9-pin, universal asynchronous receiver/transmitter (UART) serial ports  
– Two 4-pin, Universal Serial Bus ports  
– One 6-pin, keyboard port (Windows 95 compatible)  
– One 6-pin, mouse port  
– One 15-pin, DDC2B-compliant monitor port on the AGP adapter  
– Three 3.5-mm audio jacks (line out/headphone, line in, microphone)  
Other features  
The PC 300PL Personal Computer supports the following features:  
Network support  
PC 300PL Personal Computer computers are enabled to support management over a network. The  
following is a list of supported functions:  
Ÿ Selectable startup sequence  
Ÿ Selectable automatic power on startup sequence  
Ÿ POST/BIOS update from network  
Ÿ Wake on LAN feature  
Ÿ CMOS Save/Restore utility program  
Ÿ CMOS setup over LAN  
Ÿ Wake on Ring  
Wake on LAN  
The power supply of the computer supports the Wake on LAN feature. With the Wake on LAN feature,  
the computer can be turned on when a specific LAN frame is passed to the computer over the LAN.  
To use the Wake on LAN feature, the computer must be equipped with a network adapter that supports  
Wake on LAN. Some models come with a network adapter that supports Wake on LAN. You can find the  
menu for setting the Wake on LAN feature in the Configuration/Setup Utility program.  
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Technical Information Manual  
 
Chapter 1. System overview  
Wake on Ring  
All models can be configured to turn on the computer after a ring is detected from an external or internal  
modem. The menu for setting the Wake on Ring feature is in the Configuration/Setup Utility program.  
Two options control this feature:  
Ÿ Serial Ring Detect: Use this option if the computer has an external modem connected to the serial  
port.  
Ÿ Modem Ring Detect: Use this option if the computer has an internal modem.  
Chapter 1. System overview  
3
 
Chapter 2. System board features  
Chapter 2. System board features  
This section includes information about system board features. For an illustration of the system board,  
see “System board, Types 6584 and 6594” on page 13.  
Pentium III microprocessor with MMX technology  
PC 300PL Types 6584 and 6594 come with an Intel Pentium III microprocessor. The microprocessor,  
which has an attached heat sink, plugs directly into a connector on the system board.  
Features  
The features of this microprocessor are as follows:  
Ÿ Optimization for 32-bit software  
Ÿ 64-bit microprocessor data bus  
Ÿ 133 MHz front side bus (FSB)  
Ÿ 256 KB L2 cache integrated into the microprocessor  
Ÿ 32-bit microprocessor address bus  
Ÿ Math coprocessor  
Ÿ MMX technology, which boosts the processing of graphic, video, and audio data  
Ÿ Cache speed is half of processor core speed  
– 4-way set associative  
– Nonblocking  
L2 cache  
The Pentium III microprocessor provides 256 KB L2 cache. The L2 cache ECC function is automatically  
enabled if ECC memory is installed. If non-ECC memory is installed, the L2 cache ECC is disabled. (For  
information on overriding the ECC memory settings, see the chapter about the Configuration/Setup Utility  
program, in PC 300PL User Guide.) More information on this microprocessor is available at  
http://www.intel.com on the World Wide Web.  
Chip set control  
The Intel 820 chip set is the interface between the microprocessor and the following:  
Ÿ Memory subsystem  
Ÿ PCI bus  
Ÿ IDE bus master connection  
Ÿ High-performance, PCI-to-ISA bridge  
Ÿ USB ports  
Ÿ SMBus  
Ÿ Enhanced DMA controller  
Ÿ Real-time clock (RTC)  
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Copyright IBM Corp. September 1999  
 
Chapter 2. System board features  
System memory  
The system memory interface is controlled by the Intel 820 chip set. Rambus dynamic random access  
memory (RDRAM) is standard.  
The maximum amount of addressable system memory is 1 GB. For memory expansion, the system board  
provides two Rambus inline memory module (RIMM) connectors. The system board also supports PC700  
memory and PC800 memory RIMMs in sizes of 64 MB, 128 MB, 256 MB, and 512 MB. The amount of  
memory that is preinstalled varies by model.  
The following information applies to system memory:  
Ÿ ECC or non-ECC RDRAM is standard.  
Ÿ The maximum height of memory modules is 6.35 cm (2.5 in.).  
Ÿ Each memory connector supports a maximum of 512 MB of memory, when available.  
Ÿ Install only ECC RIMMS to enable ECC. If you use ECC and non-ECC memory together, all installed  
memory will function as non-ECC memory.  
Ÿ RIMM connectors do not support dual inline memory modules (DIMMs).  
Ÿ Any connector that does not have a RIMM installed must have a continuity RIMM (C-RIMM), a module  
that looks like a RIMM but has no memory on it. A continuity RIMM is used to continue the  
connection on a RIMM connector that does not have memory installed in it.  
Ÿ Use PC700 or PC800 RIMMs only.  
Ÿ Maximum system memory can be auto-detected and auto-configured using serial presence detect and  
configuration interface (BIOS specific).  
The following table shows the possible configuration of RIMMs and continuity RIMMs that can be used in  
the PC 300PL Personal Computer.  
Figure 1. Memory configurations for 133 MHz FSB  
RIMM 1  
PC700  
RIMM 2  
PC700  
Functions as  
PC700  
PC700  
PC700  
PC800  
PC800  
Invalid  
PC700  
PC800  
PC700  
C-RIMM  
PC800  
PC800  
PC800  
C-RIMM  
C-RIMM  
No RIMM  
No RIMM  
C-RIMM  
C-RIMM  
Any RIMM  
No RIMM  
No RIMM  
Invalid  
Invalid  
Invalid  
For information on the pin assignments for the memory-module connectors, see “Memory connectors” on  
page 26.  
Chapter 2. System board features  
5
 
Chapter 2. System board features  
PCI bus  
The fully synchronous 33 MHz PCI bus originates in the chip set. Features of the PCI bus are:  
Ÿ Integrated arbiter with multitransaction PCI arbitration acceleration hooks  
Ÿ Zero-wait-state, microprocessor-to-PCI write interface for high-performance graphics  
Ÿ Built-in PCI bus arbiter with support for up to five masters  
Ÿ Microprocessor-to-PCI memory write posting with 5-Dword-deep buffers  
Ÿ Conversion of back-to-back sequential microprocessor-to-PCI memory write to PCI burst write  
Ÿ PCI-to-DRAM posting 18 Dwords  
Ÿ PCI-to-DRAM up to 100+ MB/sec bandwidth  
Ÿ Multitransaction timer to support multiple short PCI transactions within one PCI ARB cycle  
Ÿ PCI 2.2 compliant  
Ÿ Delayed transaction  
Ÿ PCI parity checking and generation support  
IDE bus master interface  
The system board incorporates a PCI-to-IDE interface that complies with the AT Attachment Interface with  
Extensions.  
The bus master for the IDE interface is integrated into the I/O hub of the Intel 820 chip set. The chip set  
is PCI 2.2 compliant. It connects directly to the PCI bus and is designed to allow concurrent operations on  
the PCI bus and IDE bus. The chip set is capable of supporting PIO mode 0–4 devices and IDE DMA  
mode 0–3 devices, ATA 66 transfers up to 66 megabytes per second (MBps).  
The IDE devices receive their power through a four-position power cable containing +5, +12, and ground  
voltage. When devices are added to the IDE interface, one device is designated as the master device and  
another is designated as the slave or subordinate device. These designations are determined by switches  
or jumpers on each device. There are two IDE ports, one designated Primary and the other Secondary,  
allowing for up to four devices to be attached. The total number of physical IDE devices is determined by  
the mechanical package.  
For the IDE interface, no resource assignments are given in the system memory or the direct memory  
access (DMA) channels. For information on the resource assignments, see “Input/output address map” on  
page 36 and Figure 38 on page 40 (for IRQ assignments).  
Two connectors are provided on the riser card for the IDE interface. For information on the connector pin  
assignments, see “IDE connectors” on page 30.  
USB interface  
Universal Serial Bus (USB) technology is a standard feature of the computer. The system board provides  
the USB interface with two connectors integrated into the ICH1 (I/O hub) in the chip set. A USB-enabled  
device can attach to a connector, and if that device is a hub, multiple peripheral devices can attach to the  
hub and be used by the system. The USB connectors use Plug and Play technology for installed devices.  
The speed of the USB is up to 12 MB/sec with a maximum of 127 peripheral devices. The USB is  
compliant with Universal Host Controller Interface Guide 1.0.  
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Technical Information Manual  
 
Chapter 2. System board features  
Features provided by USB technology include:  
Ÿ Support for hot-pluggable devices  
Ÿ Support for concurrent operation of multiple devices  
Ÿ Suitability for different device bandwidths  
Ÿ Support for up to five meters length from host to hub or from hub to hub  
Ÿ Guaranteed bandwidth and low latencies appropriate for specific devices  
Ÿ Wide range of packet sizes  
Ÿ Limited power to hubs  
For information on the connector pin assignments for the USB interface, see “USB port connectors” on  
page 33.  
Low pin count bus  
The low pin count (LPC) bus allows a connection of the ISA and X-Bus devices such as Super I/O. The  
PC 300PL Personal Computer uses the National Semiconductor PC87360 Super I/O chip. The PC87360  
chip includes the following:  
Ÿ Floppy disk controller  
Ÿ Keyboard and mouse controller  
Ÿ IEEE 1284 parallel port  
Ÿ Two UART serial ports  
Ÿ Wake on LAN support  
Ÿ General purpose input/output (GPIO) ports  
Ÿ PC98 compliance  
Ÿ ACPI compliance  
Diskette write protection can be enabled or disabled by a programmable setting in the LPC I/O. This  
setting is accessible through the Configuration/Setup Utility program.  
Video subsystem  
The PC 300PL Personal Computer comes with one of the following graphics solutions:  
Ÿ NumberNine S3 Savage4 Accelerated Graphics Port (AGP) 2X adapter with 8 MB 110 MHz SDRAM  
and a 15-pin SVGA connector  
Ÿ NumberNine S3 Savage4 Extreme AGP 4X adapter, with 16 MB 166 MHz SDRAM and a converter for  
a 15-pin VGA displays  
The Savage4 graphics accelerator supports the following features:  
Ÿ 128-bit 2D graphics engine  
Ÿ High-performance 2D/3D video accelerator  
Ÿ 3D rendering  
Ÿ Motion video architecture  
Ÿ High-speed memory bus  
Ÿ Flat panel desktop monitor support  
Ÿ Full software support  
Ÿ ACPI and PCI power management  
Ÿ PCI 2.2 bus support, including bus mastering  
Ÿ 300 MHz RAMDAC with gamma correction  
Ÿ I2C serial bus and flash ROM support  
Ÿ 2.5 V core with 3.3V/5V tolerant I/O  
Ÿ Hardware and BIOS support for VESA timings and DDC monitor communications  
Chapter 2. System board features  
 
7
Chapter 2. System board features  
The video subsystem supports all video graphics array (VGA) modes and is compliant with super video  
graphics array (SVGA) modes and Video Electronics Standards Association (VESA) 1.2. Some enhanced  
features include:  
Ÿ Video subsystem on a chip, including 2D, 3D, and a video port  
Ÿ 66 MHz AGP system bus interface with 2X or 4X mode  
Ÿ Sideband signaling (some models only)  
Ÿ Command list bus mastering support for fast 2D performance  
Ÿ 64-bit, 125 MHz SDRAM or 166 MHz SGRAM interface  
Ÿ Plug and Play support  
Ÿ Advanced Power Management support  
Ÿ Color space conversion  
Ÿ Hardware scaling  
The integrated graphics memory controller subsystem supports the VESA Display Data Channel (DDC)  
standard 1.1 and uses DDC1 and DDC2B to determine optimal values during automatic monitor detection.  
The video subsystem has the following resource assignments:  
Figure 2. Video subsystem resources  
Resource  
Assignment  
ROM  
Hex C0000–C7FFF (32KB)  
RAM  
Hex A0000–BFFFF  
I/O (hex)  
VGA registers: Attributes 0–14, CRT controller 0–18/22/24/26, CRTC Extension 0-6, DACSTAT, FEAT, GCTL  
0-8, INSTS0-1, MISC, Sequencer 0-4, DAC  
IRQ  
PCI interrupt 1 (automatically assigned to IRQ 0BH by POST or can be disabled in the Configuration/Setup  
Utility)  
None  
DMA  
For further information on resource assignments, see Appendix B, “System address maps” on page 36  
and Appendix C, “IRQ and DMA channel assignments” on page 40.  
The PC 300PL Personal Computer supports the following video subsystem modes:  
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Technical Information Manual  
 
Chapter 2. System board features  
Figure 3. Supported VGA video modes  
Dot  
clock  
(MHz)  
Sweep  
rate  
(kHz)  
Mode  
(hex)  
Display  
mode  
Buffer start  
(hex)  
Refresh  
rate (Hz)  
Screen resolution  
40 x 25 characters  
40 x 25 characters  
80 x 25 characters  
80 x 25 characters  
320 x 200 pixels  
320 x 200 pixels  
640 x 200 pixels  
80 x 25 characters  
320 x 200 pixels  
640 x 200 pixels  
640 x 350 pixels  
640 x 350 pixels  
640 x 480 pixels  
640 x 480 pixels  
320 x 200 pixels  
Colors  
2
00  
01  
02  
03  
04  
05  
06  
07  
0D  
0E  
0F  
10  
11  
12  
13  
Text  
B8000  
B8000  
B8000  
B8000  
B8000  
B8000  
B8000  
B0000  
A0000  
A0000  
A0000  
A0000  
A0000  
A0000  
A0000  
28.322  
28.322  
28.322  
28.322  
25.175  
25.175  
25.175  
28.322  
25.175  
25.175  
25.175  
25.175  
25.175  
25.175  
25.175  
31.5  
31.5  
31.5  
31.5  
31.5  
31.5  
31.5  
31.5  
31.5  
31.5  
31.5  
31.5  
31.5  
31.5  
31.5  
70  
70  
70  
70  
70  
70  
70  
70  
70  
70  
70  
70  
60  
60  
70  
Text  
16  
Text  
B/W  
16  
Text  
Graphics  
Graphics  
Text  
4
4
2
Text  
Mono  
16  
Graphics  
Graphics  
Graphics  
Graphics  
Graphics  
Graphics  
Graphics  
16  
Mono  
16  
2
16  
256  
Monitor support  
The video subsystem provides a 15-pin monitor connector on the system board. For information on  
connector pin assignments, see Appendix A, “Connector pin assignments” on page 25.  
Video memory  
The video memory interface is controlled by an integrated graphics subsystem on the AGP adapter with  
up to 16 MB video RAM for 2D/3D graphics.  
Audio subsystem  
The PC 300PL Personal Computer comes with an integrated audio controller. These models are capable  
of playing and recording sounds and support SoundBlaster, Adlib, and Microsoft Windows Sound System  
applications.  
The device drivers for the preinstalled audio adapter are on the hard disk. The device drivers are also  
available on the Product Recovery CD or Device Driver and IBM Enhanced Diagnostics CD that comes  
with the computer.  
If you connect an optional device to the audio adapter, follow the instructions provided by the  
manufacturer. (Note that device drivers might be required. If necessary, contact the manufacturer for  
information on these device drivers.)  
The following connectors are available on the integrated audio controller:  
Ÿ Line/headphone out port for connecting powered speakers. To hear audio from the adapter you must  
connect a set of speakers to the Line out port. These speakers must be powered with a built-in  
amplifier. In general, any powered speakers designed for use with personal computers can be used  
with the audio subsystem. These speakers are available with a wide range of features and power  
outputs.  
Ÿ Line in port for connecting musical devices, such as a portable CD player or stereo system.  
Chapter 2. System board features  
 
9
Chapter 2. System board features  
Ÿ Microphone for connecting a microphone.  
Super input/output controller  
Control of the integrated input/output (I/O) and diskette drive controllers is provided by a single module.  
This module, which supports Plug and Play, controls the following features:  
Ÿ Diskette drive interface  
Ÿ Serial port  
Ÿ Parallel port  
Ÿ Keyboard and mouse ports  
Ÿ General-purpose I/O ports  
Diskette drive interface  
The PC 300PL Personal Computer has four drive bays for installing internal devices. The following is a  
list of devices that the diskette drive subsystem supports:  
Ÿ 1.44 MB, 3.5-inch diskette drive  
Ÿ 1.44 MB, 3.5-inch, 3-mode drive for Japan (no BIOS support for 3-mode drive)  
Ÿ 1.2 MB, 5.25-inch diskette drive  
Ÿ 1 Mbps, 500-Kbps, or 250 Kbps internal tape drive  
One connector is provided on the system board for diskette drive support. For information on the  
connector pin assignments, see “Diskette drive connector” on page 31.  
Serial ports  
Two universal asynchronous receiver/transmitter (UART) serial ports are integrated into the system  
board. The serial ports include 16-byte data, first-in first-out (FIFO) buffers and have programmable baud  
rate generators. The serial ports are NS16450 and PC16550A compatible.  
For information on the connector pin assignments, see “Serial port connector” on page 34.  
Note: Current loop interface is not supported.  
The following figure shows the serial port assignments in the configuration.  
Figure 4. Serial port assignments  
Port assignment  
Serial 1  
Address range (hex)  
03F8–03FF  
IRQ level  
IRQ4  
Serial 2  
02F8–02FF  
IRQ3  
Serial 3  
03E8–03FF  
IRQ4  
Serial 4  
02E8–02FF  
IRQ3  
The default setting for the serial port is COM1.  
Parallel port  
Integrated in the system board is support for extended capabilities port (ECP), enhanced parallel port  
(EPP), and standard parallel port (SPP) modes. The modes of operation are selected through the  
Configuration/Setup Utility program with the default mode set to SPP. The ECP and EPP modes are  
compliant with IEEE 1284.  
The following figure shows the parallel port assignments used in the configuration.  
10 Technical Information Manual  
 
Chapter 2. System board features  
Figure 5. Parallel port assignments  
Port assignment  
Parallel 1  
Address range (hex)  
03BC–03BE  
IRQ level  
IRQ7  
Parallel 2  
0378–037F  
IRQ5  
Parallel 3  
0278–027F  
IRQ5  
The default setting for the parallel port is Parallel 1.  
The system board has one connector for the parallel port. For information on the connector pin  
assignments, see “Parallel port connector” on page 34.  
Keyboard and mouse ports  
The keyboard and mouse subsystem is controlled by a general purpose 8-bit microcontroller; it is  
compatible with 8042AH. The controller consists of 256 bytes of data memory and 2 KB of read-only  
memory (ROM).  
The controller has two logical devices: one controls the keyboard and the other controls the mouse. The  
keyboard has two fixed I/O addresses and a fixed IRQ line and can operate without the mouse. The  
mouse cannot operate without the keyboard because, although it has a fixed IRQ line, the mouse relies on  
the addresses of the keyboard for operation. For the keyboard and mouse interfaces, no resource  
assignments are given in the system memory addresses or DMA channels. For information on the  
resource assignments, see “Input/output address map” on page 36 and Figure 38 on page 40 (for IRQ  
assignments).  
The system board has one connector for the keyboard port and one connector for the mouse port. For  
information on the connector pin assignments, see “Mouse and keyboard port connectors” on page 33.  
Network connection  
Some PC 300PL Personal Computer models are equipped with an Ethernet adapter and some are  
equipped with a token ring adapter that supports the Wake on LAN feature.  
Features of the Ethernet adapter are:  
Ÿ Operates in shared 10BASE-T or 100BASE-TX environment  
Ÿ Transmits and receives data at 10 Mbps or 100 Mbps  
Ÿ Has a RJ-45 connector for LAN attachment  
Ÿ Operates in symmetrical multiprocessing (SMP) environments  
Ÿ Supports Wake on LAN  
Ÿ Supports Alert on LAN  
Ÿ Supports Remote Program Load (RPL) and Dynamic Host Configuration Protocol (DHCP)  
Features of the token-ring adapter are:  
Ÿ Transmits and receives data at 4 Mbps or 16 Mbps  
Ÿ Has a RJ-45 and D-shell connectors for LAN attachment  
Ÿ Supports Wake on LAN  
Ÿ Supports Alert on LAN  
Ÿ Supports Remote Program Load (RPL) and Dynamic Host Configuration Protocol (DHCP)  
Chapter 2. System board features 11  
 
Chapter 2. System board features  
Real-time clock and CMOS  
The real-time clock is a low-power clock that provides a time-of-day clock and a calendar. The clock  
settings are maintained by an external battery source of 3 V dc.  
The system uses 242 bytes of complementary metal-oxide semiconductor (CMOS) memory to store data.  
The CMOS memory is erased if the jumper on the system board is moved.  
To locate the battery, see “System board, Types 6584 and 6594” on page 13.  
Flash EEPROM  
The system board uses 4 Megabits (Mb) of flash electrically erasable, programmable, read-only memory  
(EEPROM) to store the basic input/output system (BIOS), video BIOS, IBM logo, Configuration/Setup  
Utility, and Plug and Play data.  
If necessary, the EEPROM can be easily updated using a stand-alone utility program that is available on a  
3.5-inch diskette.  
Expansion adapters  
Each PCI-expansion connector is a 32-bit slot. PCI-expansion connectors support the 32-bit 5 V dc,  
local-bus signalling environment that is defined in PCI Local Bus Specification 2.1.  
The PC 300PL Personal Computer has four PCI slots to support the addition of adapters. For information  
on installing adapters, see PC 300PL User Guide.  
For information on the connector pin assignments, see “PCI connectors” on page 27.  
Physical layout  
The system board might look slightly different from the one shown.  
Note: A diagram of the system board, including switch and jumper settings, is attached to the underside  
of the computer cover.  
12 Technical Information Manual  
 
Chapter 2. System board features  
System board, Types 6584 and 6594  
.1/Microprocessor  
.2/RIMM connector 1  
.3/RIMM connector 2  
.4/AGP slot  
.5/Recovery jumper  
.6/Battery  
Riser card layouts  
The PC 300PL Personal Computer uses a riser card for expansion. The riser card contains expansion  
slots that connect the adapters to the peripheral component interconnect (PCI) and industry standard  
architecture (ISA) buses and connectors for the integrated drive electronics (IDE) drives and diskette  
drives. The following illustrations show the expansion slots on the riser card. The PCI slots are on the  
front of the riser card, and the power and IDE drive connectors are on the back of the riser card.  
PC 300PL — desktop model  
Some desktop models have a riser card with four PCI connector slots. The following illustration shows the  
location of the slots on the PCI riser card.  
.1/SCSI LED connector  
.2/Wake on LAN connector  
.3/Power connector (back)  
.4/Primary IDE connector (back)  
.5/Secondary IDE connector (back)  
.6/Diskette drive connector  
.7/Fan connector  
.8/Tamper detector connector  
.9/Speaker connector  
.1ð/RFID connector  
.11/Power LEDs  
.12/Alert on LAN connector  
.13/212-pin connector  
.14/CD audio connector  
.15/PCI slot 1  
.16/PCI slot 2  
.17/PCI slot 3  
.18/PCI slot 4  
Chapter 2. System board features 13  
 
Chapter 2. System board features  
Some desktop models have a riser card with two PCI slots, one ISA slot, and one shared PCI/ISA slot.  
The following illustration shows the location of the slot on the PCI/ISA riser card.  
.1/PCI slot 3  
.2/PCI slot 2  
.3/Alert on LAN connector  
.4/SCSI LED connector  
.5/Wake on LAN connector  
.6/FDD connector  
.7/Fan connector  
.8/Tamper detector connector  
.9/Speaker connector  
.1ð/RFID connector  
.11/Power LEDs  
.12/ISA slot  
.13/ISA slot  
.14/System board connector  
.15/PCI slot 1  
.16/CD audio connector  
PC 300PL — tower model  
The following illustration shows the riser card on the tower model.  
.1/PCI slots 1-5, lowest to highest  
.2/Diskette drive connector  
.3/Hard disk fan 1 connector  
.4/Hard disk fan 2 connector  
.5/Front fan connector  
.6/Wake on LAN connector  
.7/RFID connector  
.8/Speaker connector  
.9/Tamper detector connector  
.1ð/SCSI LED connector  
.11/IDE secondary connector  
.12/IDE primary connector  
.13/Power connector  
.14/Alert on LAN connector  
.15/212-pin system board connector  
.16/CD audio connector  
Recovery jumper  
The recovery jumper on the system board is used for custom configurations. For the location of the  
recovery jumper, see the “System board, Types 6584 and 6594” on page 13.  
Figure 6. Recovery jumper  
Pins  
Description  
1 and 2  
2 and 3  
Normal (factory default)  
Clear CMOS/password, boot block recovery  
Cable connectors  
Connections for attaching devices are provided on the back of the computer. The connectors are:  
Ÿ USB (2)  
Ÿ Mouse  
Ÿ Keyboard  
Ÿ Serial (2)  
Ÿ Parallel  
Ÿ Monitor (SVGA or DVI)  
Ÿ Audio connectors for line in, line/headphone out, and microphone  
14 Technical Information Manual  
 
Chapter 2. System board features  
Connector panel  
Each connector for a features that is integrated into the system board can be identified by an icon directly  
below the connector. A connectors provided by an adapter might not have an identifying icon.  
For pin-out details on connectors, see Appendix A, “Connector pin assignments” on page 25.  
The following illustration shows the connector panel for the tower model:  
.1/USB connector 2  
.2/Serial connector 2  
.3/Mouse connector  
.4/SVGA monitor connector  
.5/DVI monitor connector  
.6/Keyboard connector  
.7/Serial connector 1  
.8/USB connector 1  
.9/Parallel connector  
.1ð/Microphone connector  
.11/Line in connector  
.12/Line/headphone out connector  
The following illustration shows the connector panel for the desktop model:  
.1/USB connector 2  
.2/Serial connector 2  
.3/SVGA monitor connector  
.4/DVI monitor connector  
.5/Mouse connector  
.6/Keyboard connector  
.7/Serial connector 1  
.8/USB connector 1  
.9/Parallel connector  
.1ð/Microphone connector  
.11/Line in connector  
.12/Line/headphone out connector  
2
2
1
1
Chapter 2. System board features 15  
 
Chapter 3. Physical specifications  
Chapter 3. Physical specifications  
This section lists the physical specifications for the PC 300PL Types 6584 and 6594. The PC 300PL  
Personal Computer desktop model has four expansion slots and four drive bays. The PC 300PL Personal  
Computer tower model has six expansion slots and six drive bays.  
Note: This computer is classified as a Class B digital device. However, this computer includes a built-in  
network interface controller (NIC) and is considered a Class A digital device when the NIC is in  
use. The Class A digital device rating and compliance notice are primarily because the inclusion  
of certain Class A options or Class A NIC cables changes the overall rating of the computer to  
Class A.  
PC 300PL — desktop  
Dimensions  
Heat output  
Ÿ Height: 134 mm (5.3 in.)  
Ÿ Width: 447 mm (17.6 in.)  
Ÿ Depth: 450 mm (17.7 in.)  
Ÿ Approximate heat output in British thermal units (Btu) per  
hour:  
– Minimum configuration: 245 Btu/hr (70 watts)  
– Maximum configuration: 700 Btu/hr (204 watts)  
Weight  
Airflow  
Ÿ Minimum configuration as shipped: 10.0 kg (22 lb)  
Ÿ Maximum configuration: 11.4 kg (25 lb)  
Ÿ Approximately 0.56 cubic meter per minute (20 cubic feet  
per minute) maximum  
Environment  
Acoustical noise-emission values  
Ÿ Air temperature:  
– System on: 10° to 35°C (50° to 95°F)  
– System off: 10° to 43°C (50° to 110°F)  
– Maximum altitude: 2134 m (7000 ft)  
Ÿ Average sound-pressure levels:  
– At operator position:  
- Idle: 37 dBA  
- Operating: 43 dBA  
– At bystander position–1 meter (3.3 ft):  
- Idle: 32 dBA  
Note: The maximum altitude, 2133.6 m (7000 ft.), is  
the maximum altitude at which the specified air  
temperatures apply. At higher altitudes, the  
maximum air temperatures are lower than those  
specified.  
- Operating: 36 dBA  
Ÿ Declared (upper limit) sound-power levels:  
– Idle: 4.7 bels  
Ÿ Humidity:  
– Operating: 5.1 bels  
– System on: 8% to 80%  
– System off: 8% to 80%  
Note: These levels were measured in controlled acoustical  
environments according to procedures specified by the  
American National Standards Institute (ANSI) S12.10 and  
ISO 7779 and are reported in accordance with ISO 9296.  
Actual sound-pressure levels in a given location might  
exceed the average values stated because of room  
reflections and other nearby noise sources. The declared  
sound-power levels indicate an upper limit, below which a  
large number of computers will operate.  
Electrical input  
Ÿ Input voltage:  
– Low range:  
- Minimum: 90 V ac  
- Maximum: 137 V ac  
- Input frequency range: 57–63 Hz  
- Voltage switch setting: 115 V ac  
– High range:  
- Minimum: 180 V ac  
- Maximum: 265 V ac  
- Input frequency range: 47–53 Hz  
- Voltage switch setting: 230 V ac  
– Input kilovolt-amperes (kVA) (approximate):  
- Minimum configuration as shipped: 0.08 kVA  
- Maximum configuration: 0.28 kVA  
Note: Power consumption and heat output vary depending  
on the number and type of optional features installed  
and the power management optional features in use.  
16  
Copyright IBM Corp. September 1999  
 
Chapter 3. Physical specifications  
PC 300PL — tower  
Dimensions  
Heat output  
Ÿ Height: 492 mm (19.4 in.)  
Ÿ Width: 200 mm (7.9 in.)  
Ÿ Depth: 445 mm (17.5 in.)  
Ÿ Approximate heat output in British thermal units (Btu) per  
hour:  
– Minimum configuration: 245 Btu/hr (70 watts)  
– Maximum configuration: 969 Btu/hr (285 watts)  
Weight  
Airflow  
Ÿ Minimum configuration as shipped: 15 kg (33 lb)  
Ÿ Maximum configuration: 17.3 kg (38 lb)  
Ÿ Approximately 0.85 cubic meter per minute (30 cubic feet  
per minute) maximum  
Environment  
Acoustical noise-emission values  
Ÿ Air temperature:  
– System on: 10° to 35°C (50° to 95°F)  
– System off: 10° to 43°C (50° to 110°F)  
– Maximum altitude: 2134 m (7000 ft)  
Ÿ Average sound-pressure levels:  
– At operator position:  
- Idle: 36 dBA  
- Operating: 39 dBA  
– At bystander position–1 meter (3.3 ft):  
- Idle: 33 dBA  
- Operating: 36 dBA  
– Declared (upper limit) sound-power levels:  
- Idle: 4.7 bels  
Note: The maximum altitude, 2133.6 m (7000 ft.), is  
the maximum altitude at which the specified air  
temperatures apply. At higher altitudes, the  
maximum air temperatures are lower than those  
specified.  
Ÿ Humidity:  
- Operating: 5.0 bels  
– System on: 8% to 80%  
– System off: 8% to 80%  
Note: These levels were measured in controlled acoustical  
environments according to procedures specified by the  
American National Standards Institute (ANSI) S12.10 and  
ISO 7779 and are reported in accordance with ISO 9296.  
Actual sound-pressure levels in a given location might  
exceed the average values stated because of room  
reflections and other nearby noise sources. The declared  
sound-power levels indicate an upper limit, below which a  
large number of computers will operate.  
Electrical input  
Ÿ Input voltage:  
– Low range:  
- Minimum: 90 V ac  
- Maximum: 137 V ac  
- Input frequency range: 57–63 Hz  
- Voltage switch setting: 115 V  
– High range:  
- Minimum: 180 V ac  
- Maximum: 265 V ac  
- Input frequency range: 47–53 Hz  
- Voltage switch setting: 230 V  
– Input kilovolt-amperes (kVA) (approximate):  
- Minimum configuration as shipped: 0.08 kVA  
- Maximum configuration: 0.38 kVA  
Note: Power consumption and heat output vary depending  
on the number and type of optional features installed  
and the power management optional features in use.  
Cabling requirements for Wake on LAN adapters  
The PC 300PL Personal Computer has a 3-pin header on the system board that provides the Auxiliary 5  
volts (AUX5) and wake-up signal connections. Newer Wake on LAN adapters have a single 3-pin header  
that connects to the 3-pin header on the riser card. Some Wake on LAN adapters have two headers: a  
3-pin, right-angle header for AUX5, and a 2-pin straight header for the wake-up signal. These Wake on  
LAN adapter options include a Y-cable that has a 3-pin system board connector on one end and splits into  
the 3-pin and 2-pin connectors that connect to the adapter.  
Chapter 3. Physical specifications 17  
 
Chapter 4. Power supply  
Chapter 4. Power supply  
The power-supply requirements are supplied by 145-watt PC 300PL Personal Computer power supply.  
The power supply provides 3.3-volt power for the Pentium microprocessor and core chip set and 5-volt  
power for PCI adapters. Also included is an auxiliary 5-volt (AUX 5) supply to provide power to  
power-management circuitry and a Wake on LAN adapter. The power supply converts the ac input  
voltage into four dc output voltages and provides power for the following:  
Ÿ System board  
Ÿ Adapters  
Ÿ Internal drives  
Ÿ Keyboard and auxiliary devices  
Ÿ USB devices  
A logic signal on the power connector controls the power supply; the front panel switch is not directly  
connected to the power supply.  
The power supply connects to the system board with a 2 x 10 connector.  
Power input  
The following figure shows the power-input specifications. The power supply has a manual switch to  
select the correct input voltage.  
Figure 7. Power-input requirements  
Specification  
Measurements  
Input voltage, low range  
Input voltage, high range  
Input frequency  
100 (min) to 127 (max) V AC  
200 (min) to 240 (max) V AC  
50 Hz 3 Hz or 60 Hz 3 Hz  
Power output  
The power supply outputs shown in the following figures include the current-supply capability of all the  
connectors, including system board, DASD, PCI, and auxiliary outputs.  
Figure 8. Power-output (145 watts)  
Output voltage  
+5 volts  
Regulation  
+5% to −4%  
+5% to −5%  
+10% to −9%  
2%  
Minimum current  
1.5 A  
Maximum current  
18.0 A  
+12 volts  
0.2 A  
4.2 A  
−12 volts  
0.0 A  
0.4 A  
+3.3 volts  
0.0 A  
10.0 A  
−5 volts  
10%  
0.0 A  
0.3 A  
+5 volt (auxiliary)  
+5% to −5%  
0.0 A  
0.02 A  
Note: The total combined 3.3 V and 5 V power must not exceed 100 watts.  
18  
Copyright IBM Corp. September 1999  
 
Chapter 4. Power supply  
Figure 9. Power output (200 watts)  
Output voltage  
+5 volts  
Regulation  
Minimum current  
1.5 A  
Maximum current  
20.0 A  
+5% to -4%  
+12 volts  
5%  
0.2 A  
8.0 A  
−12 volts  
+10% to -9%  
0.0 A  
0.4 A  
−5 volts  
10%  
2%  
0.0 A  
0.3 A  
+ 3.3 volts  
+5 volts (auxiliary)  
0.0 A  
20.0 A  
5%  
0.005 A  
0.72 A  
Component outputs  
The power supply provides separate voltage sources for the system board and internal storage devices.  
The following figures show the approximate power that is provided for specific system components. Many  
components draw less current than the maximum shown.  
Figure 10. System board  
Supply voltage  
+3.3 V dc  
Maximum current  
3000 mA  
Regulation limits  
+5.0% to −5.0%  
+5.0% to −4.0%  
+5.0% to −5.0%  
+10.0% to −9.0%  
+5.0 V dc  
4000 mA  
+12.0 V dc  
−12.0 V dc  
25.0 mA  
25.0 mA  
Figure 11. Keyboard port  
Supply voltage  
Maximum current  
Regulation limits  
+5.0 V dc  
275 mA  
+5.0% to −4.0%  
Figure 12. PCI-bus adapters (per slot)  
Supply voltage  
+5.0 V dc  
Maximum current  
2000 mA  
Regulation limits  
+5.0% to −4.0%  
+5.0% to −4.0%  
+3.3 V dc  
3030 mA  
Note: For each PCI connector, the maximum power consumption is rated at 10 watts for +5 V dc and  
+3.3 V dc combined. Typical power budget assumptions use 7.5 watts per adapter. If maximum  
power is used, then the overall system configuration will be limited in performance.  
Figure 13. USB port  
Supply voltage  
Maximum current  
Regulation limits  
+5.0 V dc  
500 mA  
+5.0% to −4.0%  
Figure 14. Internal DASD  
Supply voltage  
+5.0 V dc  
Maximum current  
Regulation limits  
+5.0% to −5.0%  
+5.0% to −5.0%  
1400 mA  
+12.0 V dc  
1500 mA at startup, 400 mA when  
active  
Chapter 4. Power supply 19  
 
Chapter 4. Power supply  
Note: Some adapters and hard disk drives draw more current than the recommended limits. These  
adapters and drives can be installed in the system; however, the power supply will shut down if the  
total power used exceeds the maximum power that is available.  
Output protection  
The power supply protects against output overcurrent, overvoltage, and short circuits. See the power  
supply specifications on the previous pages for details.  
A short circuit that is placed on any dc output (between outputs or between an output and dc return)  
latches all dc outputs into a shutdown state, with no damage to the power supply. If this shutdown state  
occurs, the power supply returns to normal operation only after the fault has been removed and the power  
switch has been turned off for at least one second.  
If an overvoltage fault occurs (in the power supply), the power supply latches all dc outputs into a  
shutdown state before any output exceeds 130% of the nominal value of the power supply.  
Connector description  
The power supply for the PC 300PL Personal Computer has four 4-pin connectors for internal devices.  
The total power used by the connectors must not exceed the amount shown in “Component outputs” on  
page 19. For connector pin assignments, see Appendix A, “Connector pin assignments” on page 25.  
20 Technical Information Manual  
 
Chapter 5. System software  
Chapter 5. System software  
This section briefly describes some of the system software included with the computer.  
BIOS  
The computer uses the IBM basic input/output system (BIOS), which is stored in flash electrically erasable  
programmable read-only memory (EEPROM). Some features of the BIOS are:  
Ÿ PCI support in accordance with PCI BIOS Specification 2.2  
Ÿ Microsoft PCI IRQ Routing Table  
Ÿ Plug and Play support in accordance with Plug and Play BIOS Specification 1.1a  
Ÿ Advanced Power Management (APM) support according to APM BIOS Interface Specification 1.2  
Ÿ Wake on LAN support  
Ÿ Wake on Ring support  
Ÿ Alert on LAN support  
Ÿ Remote program load (RPL) and Dynamic Host Configuration Protocol (DHCP)  
Ÿ Startable CD-ROM support  
Ÿ Flash-over-LAN support  
Ÿ Alternate startup sequence  
Ÿ IBM look and feel, such as screen arrangements  
Ÿ ACPI (Advanced Configuration and Power Interfaces) 1.0b  
Ÿ IDE logical block addressing (LBA) support  
Ÿ LSA 2.0 support  
Ÿ LS120 support  
Ÿ DM BIOS 2.1 (DMI 2.0 compliant)  
Ÿ PC99 compliance  
Plug and Play  
Support for Plug and Play conforms to the following:  
Ÿ Plug and Play BIOS Specification 1.1a and 1.0  
Ÿ Plug and Play BIOS Extension Design Guide 1.0  
Ÿ Plug and Play BIOS Specification, Errata, and Clarifications 1.0  
Ÿ Guide to Integrating the Plug and Play BIOS Extensions with system BIOS 1.2  
Ÿ Plug and Play Kit for DOS and Windows  
POST  
IBM power-on self-test (POST) code is used. Also, initialization code is included for the on-board system  
devices and controllers.  
POST error codes include text messages for determining the cause of an error. For more information, see  
Appendix D, “Error codes” on page 41.  
Copyright IBM Corp. September 1999  
 
21  
Chapter 5. System software  
Configuration/Setup Utility program  
The Configuration/Setup Utility program provides menus for selecting options for devices, I/O ports, date  
and time, system security, start options, advanced setup, and power management.  
More information on using the Configuration/Setup Utility program is provided in PC 300PL User Guide.  
Advanced Power Management (APM)  
The PC 300PL Personal Computer computers come with built-in energy-saving capabilities. Advanced  
Power Management (APM) is a feature that reduces the power consumption of systems when they are not  
being used. When enabled, APM initiates reduced-power modes for the monitor, microprocessor, and  
hard disk drive after a specified period of inactivity.  
The BIOS supports APM 1.2. This enables the system to enter a power-managed state, which reduces  
the power drawn from the ac electrical outlet. Advanced Power Management is enabled through the  
Configuration/Setup Utility program and is controlled by the individual operating system.  
For more information on APM, see PC 300PL User Guide and Understanding Your Personal Computer.  
Advanced Configuration and Power Interface (ACPI)  
Automatic Configuration and Power Interface (ACPI) BIOS mode enables the operating system to control  
the power management features of the computer. Not all operating systems support ACPI BIOS mode.  
See the operating system documentation to determine if ACPI is supported.  
Flash update utility program  
The flash update utility program is a stand-alone program to support flash updates. This utility program  
updates the BIOS code and can change the machine readable information (MRI) to different languages.  
The flash update utility program is available on a 3.5-inch diskette.  
Diagnostic program  
The diagnostic program that comes with the PC 300PL Personal Computer computer is provided on the  
Product Recovery CD and Device Driver and IBM Enhanced Diagnostics CD. It runs independently of the  
operating system. You can use IBM Enhanced Diagnostics to diagnose and repair problems with the  
computer. You can download the latest version from  
http://www.ibm.com/pc/support/desktop/desktop_support.html on the World Wide Web. For more  
information on this diagnostic program, see PC 300PL User Guide.  
22 Technical Information Manual  
 
Chapter 6. System compatibility  
Chapter 6. System compatibility  
This chapter discusses some of the hardware, software, and BIOS compatibility issues for the computer.  
See the Compatibility Report for a list of compatible hardware and software options.  
Hardware compatibility  
This section discusses hardware, software, and BIOS compatibility issues that must be considered when  
designing application programs.  
Many of the interfaces are the same as those used by the IBM Personal Computer AT. In most cases,  
the command and status organization of these interfaces is maintained.  
The functional interfaces are compatible with the following interfaces:  
Ÿ Intel 8259 interrupt controllers (edge-triggered mode)  
Ÿ National Semiconductor NS16450 and NS16550A serial communication controllers  
Ÿ Motorola MC146818 Time of Day Clock command and status (CMOS reorganized)  
Ÿ Intel 8254 timer, driven from a 1.193 MHz clock (channels 0, 1, and 2)  
Ÿ Intel 8237 DMA controller, except for the Command and Request registers and the Rotate and Mask  
functions; the Mode register is partially supported  
Ÿ Intel 8272 or 82077 diskette drive controllers  
Ÿ Intel 8042 keyboard controller at addresses hex 0060 and hex 0064  
Ÿ All video standards using VGA, EGA, CGA, MDA, and Hercules modes  
Ÿ Parallel printer ports (Parallel 1, Parallel 2, and Parallel 3) in compatibility mode  
Use this information to develop application programs. Whenever possible, use the BIOS as an interface to  
hardware to provide maximum compatibility and portability of applications among systems.  
Hardware interrupts  
Hardware interrupts are level-sensitive for PCI interrupts. The interrupt controller clears its in-service  
register bit when the interrupt routine sends an End-of-Interrupt (EOI) command to the controller. The EOI  
command is sent regardless of whether the incoming interrupt request to the controller is active or  
inactive.  
The interrupt-in-progress latch is readable at an I/O-address bit position. This latch is read during the  
interrupt service routine and might be reset by the read operation or it might require an explicit reset.  
Note: For performance and latency considerations, designers might want to limit the number of devices  
sharing an interrupt level.  
With level-sensitive interrupts, the interrupt controller requires that the interrupt request be inactive at the  
time the EOI command is sent; otherwise, a new interrupt request will be detected. To avoid this, a  
level-sensitive interrupt handler must clear the interrupt condition (usually by a read or write operation to  
an I/O port on the device causing the interrupt). After processing the interrupt, the interrupt handler:  
1. Clears the interrupt  
2. Waits one I/O delay  
3. Sends the EOI  
Copyright IBM Corp. September 1999  
 
23  
Chapter 6. System compatibility  
4. Waits one I/O delay  
5. Enables the interrupt through the Set Interrupt Enable Flag command  
Hardware interrupt IRQ9 is defined as the replacement interrupt level for the cascade level IRQ2.  
Program interrupt sharing is implemented on IRQ2, interrupt hex 0A. The following processing occurs to  
maintain compatibility with the IRQ2 used by IBM Personal Computer products:  
1. A device drives the interrupt request active on IRQ2 of the channel.  
2. This interrupt request is mapped in hardware to IRQ9 input on the second interrupt controller.  
3. When the interrupt occurs, the system microprocessor passes control to the IRQ9 (interrupt hex 71)  
interrupt handler.  
4. This interrupt handler performs an EOI command to the second interrupt controller and passes control  
to the IRQ2 (interrupt hex 0A) interrupt handler.  
5. This IRQ2 interrupt handler, when handling the interrupt, causes the device to reset the interrupt  
request before performing an EOI command to the master interrupt controller that finishes servicing  
the IRQ2 request.  
Hard disk drives and controller  
Reading from and writing to the hard disk is initiated in the same way as in IBM Personal Computer  
products; however, new functions are supported.  
Software compatibility  
To maintain software compatibility, the interrupt polling mechanism that is used by IBM Personal Computer  
products is retained. Software that interfaces with the reset port for the IBM Personal Computer  
positive-edge interrupt sharing (hex address 02Fx or 06Fx, where x is the interrupt level) does not create  
interference.  
Software interrupts  
With the advent of software interrupt sharing, software interrupt routines must daisy chain interrupts. Each  
routine must check the function value, and if it is not in the range of function calls for that routine, it must  
transfer control to the next routine in the chain. Because software interrupts are initially pointed to  
address 0:0 before daisy chaining, check for this case. If the next routine is pointed to address 0:0 and  
the function call is out of range, the appropriate action is to set the carry flag and do a RET 2 to indicate  
an error condition.  
Machine-sensitive programs  
Programs can select machine-specific features, but they must first identify the machine and model type.  
IBM has defined methods for uniquely determining the specific machine type. The machine model byte  
can be found through Interrupt 15H, Return System Configuration Parameters function (AH)=C0H).  
24 Technical Information Manual  
 
Appendix A. Connector pin assignments  
Appendix A. Connector pin assignments  
The following figures show the pin assignments for various system board connectors.  
Monitor connector  
5
1
10  
6
15  
11  
Figure 15. Monitor port connector pin assignments—SVGA  
Pin  
1
Signal  
Red  
I/O  
O
Pin  
2
Signal  
I/O  
O
I
Green  
3
Blue  
O
4
Monitor ID 2 - Not  
used  
5
7
9
Ground  
NA  
NA  
NA  
6
Red ground  
Blue ground  
Ground  
NA  
NA  
NA  
Green ground  
+5 V, used by DDC2B  
8
10  
11  
Monitor ID 0 - Not  
used  
I
12  
14  
DDC2B serial data  
Vertical sync  
I/O  
O
13  
15  
Horizontal sync  
DDC2B clock  
O
I/O  
C1  
C2  
1
C3  
C4  
C5  
Figure 16. Monitor port connector pin assignments—DVI main pin field  
Pin  
1
Signal  
I/O  
O
Pin  
2
Signal  
I/O  
O
TMDS data 2+  
TMDS data 2/4 return  
TMDS data 4+*  
DDC data  
TMDS data 2-  
TMDS data 4-*  
DDC clock  
3
N/A  
O
4
O
5
6
I/O  
O
7
I/O  
O
8
Analog vertical sync  
TMDS data 1+  
TMDS data 3+*  
+5V power  
9
TMDS data 1-  
TMDS data 1/3 shield  
TMDS data 3+*  
Ground  
10  
12  
14  
16  
18  
20  
22  
24  
O
11  
13  
15  
17  
19  
21  
23  
N/A  
O
O
O
N/A  
O
Hot plug detect  
TMDS data 0+  
TMDS D5*  
O
TMDS data 0-  
Return  
O
N/A  
O
O
TMDS data 5+*  
TMDS clock+  
TMDS clock shield  
TMDS clock-  
N/A  
O
O
Copyright IBM Corp. September 1999  
 
25  
Appendix A. Connector pin assignments  
Figure 17. Monitor port connector pin assignments—DVI MicroCross section  
Pin  
C1  
C3  
C5  
Signal  
I/O  
O
Pin  
C2  
C4  
Signal  
I/O  
O
Red video out  
Analog blue  
Green video out  
Analog horizontal sync  
O
O
Video/pixel clock return  
N/A  
*These are not used on the NumberNine S3 Savage4 AGP card.  
Memory connectors  
93  
184  
1
92  
Figure 18 (Page 1 of 2). System memory connector pin assignments  
Pin  
A1  
Signal  
Gnd  
Pin  
B1  
Signal  
Gnd  
Pin  
Signal  
Pin  
Signal  
NC  
A47  
A48  
A49  
A50  
A51  
A52  
A53  
A54  
A55  
A56  
A57  
A58  
A59  
A60  
A61  
A62  
A63  
A64  
A65  
A66  
A67  
A68  
A69  
A70  
A71  
A72  
A73  
A74  
NC  
B47  
B48  
B49  
B50  
B51  
B52  
B53  
B54  
B55  
B56  
B57  
B58  
B59  
B60  
B61  
B62  
B63  
B64  
B65  
B66  
B67  
B68  
B69  
B70  
B71  
B72  
B73  
B74  
A2  
LDQA8  
Gnd  
B2  
LDQA7  
Gnd  
NC  
NC  
A3  
B3  
NC  
NC  
A4  
LDQA6  
Gnd  
B4  
LDQA5  
Gnd  
NC  
NC  
A5  
B5  
Vref  
Vref  
A6  
LDQA4  
Gnd  
B6  
LDQA3  
Gnd  
Gnd  
Gnd  
A7  
B7  
SCL  
SA0  
A8  
LDQA2  
Gnd  
B8  
LDQA1  
Gnd  
Vdd  
Vdd  
A9  
B9  
SDA  
SA1  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
A27  
A28  
LDQA0  
Gnd  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
B19  
B20  
B21  
B22  
B23  
B24  
B25  
B26  
B27  
B28  
LCFM  
Gnd  
SVdd  
SWP  
Vdd  
SVdd  
SA2  
LCTMN  
Gnd  
LCFMN  
Gnd  
Vdd  
RSCK  
Gnd  
RCMD  
Gnd  
LCTM  
Gnd  
NC  
Gnd  
RDQB7  
Gnd  
RDQB8  
Gnd  
NC  
LROW2  
Gnd  
Gnd  
RDQB5  
Gnd  
RDQB6  
Gnd  
LROW1  
Gnd  
LROW0  
Gnd  
RDQB3  
Gnd  
RDQB4  
Gnd  
LCOL4  
Gnd  
LCOL3  
Gnd  
RDQB1  
Gnd  
RDQB2  
Gnd  
LCOL2  
Gnd  
LCOL1  
Gnd  
RCOL0  
Gnd  
RDQB0  
Gnd  
LCOL0  
Gnd  
LDQB0  
Gnd  
RCOL2  
Gnd  
RCOL1  
Gnd  
LDQB1  
Gnd  
LDQB2  
Gnd  
RCOL4  
Gnd  
RCOL3  
Gnd  
LDQB3  
LDQB4  
26 Technical Information Manual  
 
Appendix A. Connector pin assignments  
Figure 18 (Page 2 of 2). System memory connector pin assignments  
Pin  
Signal  
Gnd  
Pin  
Signal  
Gnd  
Pin  
Signal  
RROW1  
Gnd  
Pin  
Signal  
RROW0  
Gnd  
A29  
A30  
A31  
A32  
A33  
A34  
A3  
B29  
B30  
B31  
B32  
B33  
B34  
B35  
B36  
B37  
B38  
B39  
B40  
B41  
B42  
B43  
B44  
B45  
B46  
A75  
A76  
A77  
A78  
A79  
A80  
A81  
A82  
A83  
A84  
A85  
A86  
A87  
A88  
A89  
A90  
A91  
A92  
B75  
B76  
B77  
B78  
B79  
B80  
B81  
B82  
B83  
B84  
B85  
B86  
B87  
B88  
B89  
B90  
B91  
B92  
LDQB5  
Gnd  
LDQB6  
Gnd  
NC  
RROW2  
Gnd  
LDQB7  
Gnd  
LDQB8  
Gnd  
Gnd  
RCTM  
Gnd  
NC  
LSCK  
Vcmos  
SOUT  
Vcmos  
NC  
LCMD  
Vcmos  
SIN  
Gnd  
RCTMN  
Gnd  
RCFMN  
Gnd  
A36  
A37  
A38  
A39  
A40  
A41  
A42  
A43  
A44  
A45  
A46  
Vcmos  
NC  
RDQA0  
Gnd  
RCFM  
Gnd  
Gnd  
Gnd  
RDQA2  
Gnd  
RDQA1  
Gnd  
NC  
NC  
Vdd  
Vdd  
RDQA4  
Gnd  
RDQA3  
Gnd  
Vdd  
Vdd  
NC  
NC  
RDQA6  
Gnd  
RDQA5  
Gnd  
NC  
NC  
NC  
NC  
RDQA8  
Gnd  
RDQA7  
Gnd  
NC  
NC  
PCI connectors  
A1  
B2  
A62  
B62  
A2  
B1  
Figure 19 (Page 1 of 3). PCI connector pin assignments  
Pin  
A1  
Signal  
I/O  
O
Pin  
B1  
Signal  
I/O  
TRST#  
+12 V dc  
TMS  
−12 V dc  
NA  
O
A2  
NA  
O
B2  
TCK  
A3  
B3  
Ground  
TDO  
NA  
I
A4  
TDI  
O
B4  
A5  
+5 V dc  
INTA#  
NA  
I
B5  
+5 V dc  
+5 V dc  
INTB#  
NA  
NA  
I
A6  
B6  
A7  
INTC#  
I
B7  
A8  
+5 V dc  
Reserved  
+5 V dc  
Reserved  
Ground  
Ground  
3.3 V AUX  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
B8  
INTD#  
I
A9  
B9  
PRSNT1#  
Reserved  
PRSNT2#  
Ground  
Ground  
3.3 V AUX  
I
A10  
A11  
A12  
A13  
A14  
B10  
B11  
B12  
B13  
B14  
NA  
I
NA  
NA  
NA  
Appendix A. Connector pin assignments 27  
 
Appendix A. Connector pin assignments  
Figure 19 (Page 2 of 3). PCI connector pin assignments  
Pin  
Signal  
I/O  
O
Pin  
Signal  
I/O  
NA  
O
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
A27  
A28  
A29  
A30  
A31  
A32  
A33  
A34  
A35  
A36  
A37  
A38  
A39  
A40  
A41  
A42  
A43  
A44  
A45  
A46  
A47  
A48  
A49  
A50  
A51  
A52  
A53  
A54  
A55  
A56  
A57  
RST#  
B15  
B16  
B17  
B18  
B19  
B20  
B21  
B22  
B23  
B24  
B25  
B26  
B27  
B28  
B29  
B30  
B31  
B32  
B33  
B34  
B35  
B36  
B37  
B38  
B39  
B40  
B41  
B42  
B43  
B44  
B45  
B46  
B47  
B48  
B49  
B50  
B51  
B52  
B53  
B54  
B55  
B56  
B57  
Ground  
+5 V dc (I/O)  
GNT#  
NA  
O
CLK  
Ground  
NA  
I
Ground  
NA  
NA  
I/O  
NA  
I/O  
I/O  
I/O  
I/O  
O
REQ#  
PCI  
+5 V dc  
NA  
I/O  
I/O  
NA  
I/O  
NA  
NA  
I/O  
I/O  
NA  
I/O  
NA  
NA  
I/O  
I/O  
NA  
I/O  
NA  
I/O  
NA  
I/O  
I/O  
NA  
I/O  
NA  
I/O  
I/O  
NA  
I/O  
I/O  
NA  
NA  
NA  
I/O  
I/O  
NA  
I/O  
I/O  
NA  
Address/data 30  
+3.3 V dc  
Address/data 28  
Address/data 26  
Ground  
Address/data 31  
Address/data 29  
Ground  
Address/data 27  
Address/data 25  
+3.3 V dc  
C/BE 3#  
Address/data 24  
IDSEL  
+3.3 V dc  
Address/data 22  
Address/data 20  
Ground  
NA  
I/O  
I/O  
I/O  
I/O  
I/O  
NA  
I/O  
NA  
I/O  
NA  
I/O  
NA  
I/O  
I/O  
NA  
NA  
I/O  
I/O  
NA  
I/O  
I/O  
NA  
NA  
NA  
I/O  
I/O  
NA  
I/O  
I/O  
NA  
Address/data 23  
Ground  
Address/data 21  
Address/data 19  
+3.3 V dc  
Address/data 17  
C/BE 2#  
Address/data 18  
Address/data 16  
+3.3 V dc  
FRAME#  
Ground  
Ground  
IRDY#  
TRDY#  
+3.3 V dc  
DEVSEL#  
Ground  
Ground  
STOP#  
+3.3 V dc  
SMBCLK*  
SMBDATA*  
Ground  
LOCK#  
PERR#  
+3.3 V dc  
SERR#  
PAR  
+3.3 V dc  
C/BE 1#  
Address/data 15  
3.3 V dc  
Address/data 14  
Ground  
Address/data 13  
Address/data 11  
Ground  
Address/data 12  
Address/data 10  
Ground  
Address/data 9  
Key  
Key  
Key  
Key  
C/BE(0)#  
Address/data 8  
Address/data 7  
+3.3 V dc  
Address/data 5  
Address/data 3  
Ground  
3.3 V dc  
Address/data 6  
Address/data 4  
Ground  
Address/data 2  
28 Technical Information Manual  
 
Appendix A. Connector pin assignments  
Figure 19 (Page 3 of 3). PCI connector pin assignments  
Pin  
Signal  
I/O  
I/O  
NA  
I/O  
NA  
NA  
Pin  
Signal  
I/O  
I/O  
NA  
I/O  
NA  
NA  
A58  
A59  
A60  
A61  
A62  
Address/data 0  
+5 V dc  
B58  
B59  
B60  
B61  
B62  
Address/data 1  
+5 V dc  
ACK64#  
+5 V dc  
ACK64#  
+5 V dc  
+5 V dc  
+5 V dc  
*These assignments are for PCI connector slot one only; for all other slots, the signal for pin A40 is  
SDONE and for pin A41 is SBO#.  
ISA connectors  
A1  
A31 C1  
B31 D1  
C18  
D18  
B1  
Note: The ISA connectors are on the riser card.  
Figure 20 (Page 1 of 2). ISA connector pin assignments  
Pin  
B1  
Signal  
Ground  
RESET DRV  
+5 V dc  
IRQ2  
I/O  
NA  
O
NA  
I
Pin  
A1  
Signal  
IOCHCK#  
SD7  
I/O  
I
B2  
A2  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
B3  
A3  
SD6  
B4  
A4  
SD5  
B5  
-5 V dc  
DRQ2  
NA  
I
A5  
SD4  
B6  
A6  
SD3  
B7  
-12 V dc  
OWS#  
NA  
I
A7  
SD2  
B8  
A8  
SD1  
B9  
+12 V dc  
Ground  
SMEMW#  
SMEMR#  
IOW#  
NA  
NA  
O
O
I/O  
I/O  
O
I
A9  
SD0  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
B19  
B20  
B21  
B22  
B23  
B24  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
IOCHRDY  
AEN  
O
SA19  
SA18  
SA17  
SA16  
SA15  
SA14  
SA13  
SA12  
SA11  
SA10  
SA9  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
IOR#  
DACK3#  
DRQ3  
DACK1#  
DRQ1  
O
I
REFRESH#  
CLK  
I/O  
O
I
IRQ7  
IRQ6  
I
IRQ5  
I
SA8  
IRQ4  
I
SA7  
Appendix A. Connector pin assignments 29  
 
Appendix A. Connector pin assignments  
Figure 20 (Page 2 of 2). ISA connector pin assignments  
Pin  
B25  
B26  
B27  
B28  
B29  
B30  
B31  
D1  
Signal  
IRQ3  
I/O  
Pin  
A25  
A26  
A27  
A28  
A29  
A30  
A31  
C1  
Signal  
SA6  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
DACK2#  
TC  
O
O
O
NA  
O
NA  
I
SA5  
SA4  
BALE  
SA3  
+5 V dc  
OSC  
SA2  
SA1  
Ground  
MEMCS16#  
IOCS16#  
IRQ10  
SA0  
SBHE#  
LA23  
LA22  
LA21  
LA20  
LA19  
LA18  
LA17  
MEMR#  
MEMW#  
SD8  
D2  
I
C2  
D3  
I
C3  
D4  
IRQ11  
I
C4  
D5  
IRQ12  
I
C5  
D6  
IRQ15  
I
C6  
D7  
IRQ14  
I
C7  
D8  
DACK0#  
DRQ0  
O
I
C8  
D9  
C9  
D10  
D11  
D12  
D13  
D14  
D15  
D16  
D17  
D18  
DACK5#  
DRQ5  
O
I
C10  
C11  
C12  
C13  
C14  
C15  
C16  
C17  
C18  
DACK6#  
DRQ6  
O
I
SD9  
SD10  
SD11  
SD12  
SD13  
SD14  
SD15  
DACK7#  
DRQ7  
O
I
+5 V DC  
MASTER#  
Ground  
NA  
I
NA  
IDE connectors  
2
1
40  
39  
Figure 21 (Page 1 of 2). IDE connector pin assignments  
Pin  
1
Signal  
I/O  
O
Pin  
21  
22  
23  
24  
25  
26  
27  
28  
Signal  
NC  
I/O  
NA  
NA  
O
RESET  
2
Ground  
NA  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
Ground  
I/O write  
NC  
3
Data bus bit 7  
Data bus bit 8  
Data bus bit 6  
Data bus bit 9  
Data bus bit 5  
Data bus bit 10  
4
NA  
O
5
I/O read  
Ground  
6
NA  
I
7
I/O channel ready  
ALE  
8
O
30 Technical Information Manual  
 
Appendix A. Connector pin assignments  
Figure 21 (Page 2 of 2). IDE connector pin assignments  
Pin  
9
Signal  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NA  
NA  
Pin  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
Signal  
NC  
I/O  
NA  
NA  
I
Data bus bit 4  
Data bus bit 11  
Data bus bit 3  
Data bus bit 12  
Data bus bit 2  
Data bus bit 13  
Data bus bit 1  
Data bus bit 14  
Data bus bit 0  
Data bus bit 15  
Ground  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Ground  
IRQ  
CS16#  
SA1  
I
O
I
PDIAG#  
SA0  
O
O
O
O
I
SA2  
CS0#  
CS1  
Active#  
Ground  
Key (Reserved)  
NA  
Diskette drive connector  
Figure 22. Diskette drive connector pin assignments  
Pin  
1
Signal  
I/O  
I
Pin  
2
Signal  
I/O  
O
NA  
NA  
I
Drive 2 installed #  
Not connected  
Ground  
High density select  
Not connected  
Data rate 0  
3
NA  
NA  
NA  
NA  
NA  
NA  
NA  
I
4
5
6
7
Ground  
8
Index#  
9
Reserved  
Ground  
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
Motor enable 0#  
Drive select 1#  
Drive select 0#  
Motor enable 1#  
Direction in#  
Step#  
O
O
O
O
O
O
O
O
I
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
Ground  
Ground  
MSEN1  
Ground  
NA  
NA  
NA  
NA  
I
Ground  
Write data#  
Ground  
Write enable#  
Track0#  
Ground  
MSEN0  
Write protect#  
Read data#  
I
Ground  
NA  
NA  
NA  
I
Ground  
Head 1 select#  
Diskette change#  
O
I
Data rate 1  
Power supply connector  
Figure 23 (Page 1 of 2). Power supply connector pin assignments  
Pin  
1
Signal name  
+3.3 V  
Pin  
11  
Signal name  
+3.3 V  
2
+3.3 V  
12  
−12 V  
Appendix A. Connector pin assignments 31  
 
Appendix A. Connector pin assignments  
Figure 23 (Page 2 of 2). Power supply connector pin assignments  
Pin  
3
Signal name  
Ground  
Pin  
13  
14  
15  
16  
17  
18  
19  
20  
Signal name  
Ground  
ON/OFF  
Ground  
Ground  
Ground  
−5 V  
4
+5 V  
5
Ground  
6
+5 V  
7
Ground  
8
PWR GOOD  
+5 V standby  
+12 V  
9
+5 V  
10  
+5 V  
Wake on LAN connectors  
Figure 24. Wake on LAN connector pin assignments  
Pin  
1
Description  
+5 V standby  
Ground  
2
3
Wake on LAN  
Alert on LAN connectors  
Figure 25. Alert on LAN connector pin assignments  
Pin  
1
Description  
SMB Data  
SMB Clock  
Intrusion  
2
3
Tamper detection switch  
Figure 26. Tamper switch pin assignments  
Pin  
1
Description  
Ground  
2
Tamper switch  
Radio frequency ID  
Figure 27. Radio frequency identification (RFID) pin assignments  
Pin  
1
Description  
RFID Ant 1  
Key  
2
3
Ground  
4
RFID Ant 2  
32 Technical Information Manual  
 
Appendix A. Connector pin assignments  
SCSI high frequency LED connectors  
Figure 28. SCSI high frequency LED connector pin assignments  
Pin  
1
Description  
Not connected  
to LED  
2
3
to LED  
4
Not connected  
CD audio connector  
Figure 29. CD audio connector pin assignments  
Pin  
1
Description  
CD in left  
2
CD in Ground  
CD in Ground  
CD in Right  
3
4
USB port connectors  
2
4
1
3
Figure 30. USB port connector pin assignments  
Pin  
1
Signal  
VCC  
2
-Data  
3
+Data  
Ground  
4
Mouse and keyboard port connectors  
6
4
5
3
1
2
Figure 31 (Page 1 of 2). Mouse port connector pin assignments  
Pin  
1
Signal  
Data  
I/O  
I/O  
NA  
Pin  
2
Signal  
I/O  
I/O  
NA  
Reserved  
+5 V dc  
3
Ground  
4
Appendix A. Connector pin assignments 33  
 
Appendix A. Connector pin assignments  
Figure 31 (Page 2 of 2). Mouse port connector pin assignments  
Pin  
Signal  
I/O  
Pin  
Signal  
I/O  
5
Clock  
I/O  
6
Reserved  
NA  
Figure 32. Keyboard port connector pin assignments  
Pin  
1
Signal  
I/O  
I/O  
NA  
I/O  
Pin  
2
Signal  
I/O  
I/O  
NA  
I/O  
Keyboard data  
Ground  
Mouse data  
+5 V dc  
3
4
5
Keyboard clock  
6
Mouse clock  
Serial port connector  
5
1
6
9
Figure 33. Serial port connector pin assignments  
Pin  
1
Signal  
I/O  
I
Pin  
2
Signal  
I/O  
Data carrier detect  
Transmit data#  
Ground  
Receive data#  
Data terminal read  
Data set ready  
Clear to send  
I
3
O
NA  
O
I
4
O
I
5
6
7
Request to send  
Ring indicator  
8
I
9
Parallel port connector  
1
13  
25  
14  
Figure 34 (Page 1 of 2). Parallel port connector pin assignments  
Pin  
1
Signal  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
Pin  
2
Signal  
I/O  
I/O  
I/O  
I/O  
I/O  
I
STROBE#  
Data bit 1  
Data bit 3  
Data bit 5  
Data bit 7  
BUSY  
Data bit 0  
Data bit 2  
Data bit 4  
Data bit 6  
ACK#  
3
4
5
6
7
8
9
10  
12  
14  
16  
18  
20  
22  
24  
11  
13  
15  
17  
19  
21  
23  
PE  
I
SLCT  
I
AUTO FD XT#  
INIT#  
O
ERROR#  
SLCT IN#  
Ground  
I
O
O
Ground  
Ground  
Ground  
Ground  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
Ground  
Ground  
34 Technical Information Manual  
 
Appendix A. Connector pin assignments  
Figure 34 (Page 2 of 2). Parallel port connector pin assignments  
Pin  
Signal  
I/O  
Pin  
Signal  
I/O  
25  
Ground  
NA  
Appendix A. Connector pin assignments 35  
 
Appendix B. System address maps  
Appendix B. System address maps  
System memory map  
The first 640 KB of system board RAM is mapped starting at address hex 0000000. A 256 byte area and  
a 1 KB area of this RAM are reserved for BIOS data areas. Memory can be mapped differently if POST  
detects an error.  
Figure 35. System memory map  
Address range (decimal)  
0 K – 512 K  
Address range (hex)  
00000–7FFFF  
Size  
Description  
512 KB  
127 KB  
1 KB  
Conventional  
512 K – 639 K  
80000–9FBFF  
Extended conventional  
Extended BIOS data  
639 K – 640 K  
9FC00–9FFFF  
A0000–BFFFF  
640 K – 767 K  
128 KB  
Dynamic video memory  
display cache  
768 K – 800 K  
800 K – 896 K  
896 K – 1 MB  
C0000 to C7FFF  
C8000–DFFFF  
E0000–FFFFF  
32 KB  
96 KB  
128 KB  
Video ROM BIOS  
(shadowed)  
PCI space, available to  
adapter ROMs  
System ROM BIOS (main  
memory shadowed)  
1 MB – 16 MB  
100000–FFFFFF  
15 MB  
PCI space  
16 MB – 4095.872 MB  
1000000–FFDFFFF  
FFFE0000 – FFFFFFFF  
4079.8 MB  
128 KB  
PCI space (positive decode)  
System ROM BIOS  
Input/output address map  
The following figure lists resource assignments for the I/O address map. Any addresses that are not  
shown are reserved.  
Figure 36 (Page 1 of 3). I/O address map  
Address (Hex)  
0000–000F  
0010–001F  
0020–0021  
0022–003F  
0040–0043  
0044–00FF  
0060  
Size  
Description  
16 bytes  
16 bytes  
2 bytes  
30 bytes  
4 bytes  
28 bytes  
1 byte  
1 byte  
1 byte  
1 bit  
DMA 1  
General I/O locations — available to PCI bus  
Interrupt controller 1  
General I/0 locations — available to PCI bus  
Counter/timer 1  
General I/0 locations — available to PCI bus  
Keyboard controller byte - reset IRQ  
PIIX4, system port B  
0061  
0064  
Keyboard controller, CMD/STAT byte  
Enable NMI  
0070, bit 7  
0070, bits 6:0  
0071  
1 bit  
Real-time clock, address  
1 byte  
14 bytes  
1 byte  
1 byte  
Real-time clock, data  
0072–007F  
0080  
General I/O locations — available to PCI bus  
POST checkpoint register during POST only  
Refresh page register  
008F  
36  
Copyright IBM Corp. September 1999  
 
Appendix B. System address maps  
Figure 36 (Page 2 of 3). I/O address map  
Address (Hex)  
0080–008F  
0090–0091  
0092  
Size  
Description  
16 bytes  
15 bytes  
1 byte  
ICH1, DMA page registers  
General I/O locations — available to PCI bus  
PS/2 keyboard controller registers  
0093–009F  
00A0–00A1  
00A2–00BF  
00C0–00DF  
00E0–00EF  
00F0  
15 bytes  
2 bytes  
30 bytes  
31 bytes  
16 bytes  
1 byte  
General I/O locations  
Interrupt controller 2  
APM control  
DMA 2  
General I/O locations — available to PCI bus  
BX, Coprocessor Error register  
00F1–016F  
0170–0177  
01F0–01F7  
0200–0207  
0220–0227  
0228–0277  
0278–027F  
0280–02E7  
02E8–02EF  
02F8–02FF  
0338–033F  
0340–036F  
0370–0371.  
0372–0375  
0376–0377  
0378–037F  
0380–03B3  
03B4–03B7  
03BA  
127 bytes  
8 bytes  
8 bytes  
8 bytes  
8 bytes  
80 bytes  
8 bytes  
102 bytes  
8 bytes  
8 bytes  
8 bytes  
48 bytes  
2 bytes  
4 bytes  
2 bytes  
8 bytes  
52 bytes  
4 bytes  
1 byte  
General I/O locations — available to PCI bus  
Secondary IDE channel  
Primary IDE channel  
Available  
SMC 37C673, Serial port 3 or 4  
General I/O locations — available to PCI bus  
SMC 27C673, LPT3  
Available  
SMC PC37C673, Serial port 3 or 4  
COM2  
SMC PC37C673, serial port 3 or 4  
Available  
SMC SIO system board Plug and Play index/data registers  
Available  
IDE channel 1 command  
LPT2  
Available  
Video  
Video  
03BC–03BE  
03C0–03CF  
03D4–03D7  
03DA  
16 bytes  
16 bytes  
4 bytes  
1 byte  
LPT1  
Video  
Video  
Video  
03D0–03DF  
03E0–03E7  
03E8–03EF  
03F0–03F5  
03F6  
11 bytes  
8 bytes  
8 bytes  
6 bytes  
1 byte  
Available  
Available  
COM3 or COM4  
Diskette channel 1  
Primary IDE channel command port  
Diskette channel 1 command  
Diskette disk change channel  
Primary IDE channel status port  
COM1  
03F7 (Write)  
03F7, bit 7  
03F7, bits 6:0  
03F8–03FF  
0400–047F  
0480–048F  
1 byte  
1 bit  
7 bits  
8 bytes  
128 bytes  
16 bytes  
Available  
DMA channel high page registers  
Appendix B. System address maps 37  
 
Appendix B. System address maps  
Figure 36 (Page 3 of 3). I/O address map  
Address (Hex)  
0490–0CF7  
0CF8–0CFB  
0CFC–0CFF  
LPTn + 400h  
0CF9  
Size  
Description  
1912 bytes  
4 bytes  
4 bytes  
8 bytes  
1 byte  
Available  
PCI Configuration address register  
PCI Configuration data register  
ECP port, LPTn base address + hex 400  
Turbo and reset control register  
Available  
0D00–FFFF  
62207 bytes  
DMA I/O address map  
The following figure lists resource assignments for the DMA address map. Any addresses that are not  
shown are reserved.  
Figure 37 (Page 1 of 2). DMA I/O address map  
Address (hex)  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
000A  
000B  
000C  
000D  
000E  
000F  
0081  
0082  
0083  
0087  
0089  
008A  
008B  
008F  
00C0  
00C2  
00C4  
00C6  
00C8  
Description  
Bits  
Byte pointer  
Yes  
Channel 0, Memory Address register  
Channel 0, Transfer Count register  
Channel 1, Memory Address register  
Channel 1, Transfer Count register  
Channel 2, Memory Address register  
Channel 2, Transfer Count register  
Channel 3, Memory Address register  
Channel 3, Transfer Count register  
Channels 0–3, Read Status/Write Command register  
Channels 0–3, Write Request register  
Channels 0–3, Write Single Mask register bits  
Channels 0–3, Mode register (write)  
Channels 0–3, Clear byte pointer (write)  
Channels 0–3, Master clear (write)/temp (read)  
Channels 0–3, Clear Mask register (write)  
Channels 0–3, Write All Mask register bits  
00–15  
00–15  
00–15  
00–15  
00–15  
00–15  
00–15  
00–15  
00–07  
00–02  
00–02  
00–07  
N/A  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
00–07  
00–03  
00–03  
00–07  
00–07  
00–07  
00–07  
00–07  
00–07  
00–07  
00–07  
00–15  
00–15  
00–15  
00–15  
00–15  
2
Channel 2, Page Table Address register  
2
Channel 3, Page Table Address register  
2
Channel 1, Page Table Address register  
2
Channel 0, Page Table Address register  
2
Channel 6, Page Table Address register  
2
Channel 7, Page Table Address register  
2
Channel 5, Page Table Address register  
Channel 4, Page Table Address/Refresh register  
Channel 4, Memory Address register  
Channel 4, Transfer Count register  
Channel 5, Memory Address register  
Channel 5, Transfer Count register  
Channel 6, Memory Address register  
Yes  
Yes  
Yes  
Yes  
Yes  
38 Technical Information Manual  
 
Appendix B. System address maps  
Figure 37 (Page 2 of 2). DMA I/O address map  
Address (hex)  
00CA  
Description  
Bits  
Byte pointer  
Channel 6, Transfer Count register  
00–15  
00–15  
00–15  
00–07  
00–02  
00–02  
00–07  
N/A  
Yes  
Yes  
Yes  
00CC  
00CE  
Channel 7, Memory Address register  
Channel 7, Transfer Count register  
00D0  
Channels 4–7, Read Status/Write Command register  
Channels 4–7, Write Request register  
Channels 4–7, Write Single Mask register bit  
Channels 4–7, Mode register (write)  
Channels 4–7, Clear byte pointer (write)  
Channels 4–7, Master clear (write)/temp (read)  
Channels 4–7, Clear Mask register (write)  
Channels 4–7, Write All Mask register bits  
Channels 5–7, 8- or 16-bit mode select  
00D2  
00D4  
00D6  
00D8  
00DA  
00–07  
00–03  
00–03  
00–07  
00DC  
00DE  
00DF  
PCI configuration space map  
Bus number (hex)  
Device number  
(hex)  
Function number  
(hex)  
Description  
00  
00  
00  
00  
01  
1E  
00  
00  
0
Intel 84440BX (host bridge)  
Intel 84440BX (PCI/AGP)  
Intel 82371AB Hub interface to PCI bridge  
registers  
00  
00  
00  
00  
02  
1F  
1F  
1F  
1F  
X
01  
02  
0
Intel 82371AB IDE bus master  
Intel 82371AB USB  
Intel 82371AB Interface bridge registers  
AC '97 audio controller  
5
00  
PCI connectors  
2
Upper byte of memory address register.  
Appendix B. System address maps 39  
 
Appendix C. IRQ and DMA channel assignments  
Appendix C. IRQ and DMA channel assignments  
The following figures list the interrupt request (IRQ) and direct memory access (DMA) channel  
assignments.  
Figure 38. IRQ channel assignments  
IRQ  
NMI  
SMI  
0
System resource  
Critical system error  
System management interrupt — power management  
Reserved (interval timer)  
Reserved (keyboard)  
Reserved, cascade interrupt from slave PIC  
COM2 3  
1
2
3
4
COM1 3  
5
LPT2/audio (if present)  
Diskette controller  
6
7
LPT1 3  
8
Real-time clock  
9
Video  
10  
11  
12  
13  
14  
15  
Available to user  
Available to user  
Mouse port  
Reserved (math coprocessor)  
Primary IDE (if present)  
Secondary IDE (if present)  
Figure 39. DMA channel assignments  
DMA channel  
Data width  
8 bits  
System resource  
0
1
2
3
4
5
6
7
Open  
8 bits  
Open  
8 bits  
Diskette drive  
8 bits  
Parallel port (for ECP or EPP)  
–
Reserved (cascade channel)  
16 bits  
16 bits  
16 bits  
Open  
Open  
Open  
3
Default, can be changed to another IRQ.  
40  
Copyright IBM Corp. September 1999  
 
Appendix D. Error Codes  
Appendix D. Error codes  
A complete list of POST error codes is provided in the PC 300PL User Guide and in the Hardware  
Maintenance Manual.  
POST error codes  
POST error messages appear when POST finds problems with the hardware during power-on or when a  
change in the hardware configuration is found. POST error messages are 3-, 4-, 5-, 8-, or 12-character  
alphanumeric messages.  
Beep codes  
A complete list of beep codes is provided in the Hardware Maintenance Manual.  
Copyright IBM Corp. September 1999  
 
41  
Appendix E. Notices and trademarks  
Appendix E. Notices and trademarks  
References in this publication to IBM products, programs, or services do not imply that IBM intends to  
make these available in all countries in which IBM operates. Any reference to an IBM product, program,  
or service is not intended to state or imply that only that IBM product, program, or service may be used.  
Subject to IBM’s valid intellectual property or other legally protectable rights, any functionally equivalent  
product, program, or service may be used instead of the IBM product, program, or service. The evaluation  
and verification of operation in conjunction with other products, except those expressly designated by IBM,  
are the responsibility of the user.  
IBM may have patents or pending patent applications covering subject matter in this document. The  
furnishing of this document does not give you any license to these patents. You can send license  
inquiries, in writing, to:  
IBM Director of Licensing  
IBM Corporation  
North Castle Drive  
Armonk, NY 10504-1785  
U.S.A.  
Any references in this publication to non-IBM Web sites are provided for convenience only and do not in  
any manner serve as an endorsement of those Web sites. The materials at those Web sites are not part  
of the materials for this IBM product and use of those Web sites is at your own risk.  
The following terms are trademarks of the IBM Corporation in the United States or other countries or both:  
Alert on LAN  
IBM  
PC 300  
PS/2  
LANClient Control Manager Wake on LAN  
Intel, Pentium, and MMX are trademarks of Intel Corporation in the United States, other countries, or both.  
Microsoft, Windows, and Windows NT are trademarks of Microsoft Corporation in the United States, other  
countries, or both.  
Other company, product, and service names may be trademarks or service marks of others.  
42  
Copyright IBM Corp. September 1999  
 
References  
Ÿ Advanced Power Management (APM) BIOS  
Interface Specification 1.2/  
Ÿ PCI BIOS Specification 2.0  
Source: PCI Special Interest Group  
Source: Intel Corporation  
Ÿ PCI Local Bus Specification 2.1  
Ÿ AT Attachment Interface with Extensions  
Source: American National Standard of Accredited  
Standards Committee  
Source: PCI Special Interest Group  
Ÿ Plug and Play BIOS Specification 1.1  
Source: Microsoft Corporation; available at  
http://www.microsoft.com/hwdev  
Ÿ Extended Capabilities Port: Specification Kit  
Source: Microsoft Corporation  
Ÿ Plug and Play BIOS Specification, Errata and  
Clarifications 1.0  
Ÿ Intel Microprocessor and Peripheral Component  
Literature  
Source: Microsoft Corporation  
Source: Intel Corporation  
Ÿ Universal Serial Bus Specifications  
Source: http://www.usb.org  
Ÿ Video Electronics Standards Association 1.2  
Source: http://www.vesa.org  
Ÿ AT24RF08A- PCID Specification  
Copyright IBM Corp. September 1999  
43  
 
Index  
Index  
connector (continued)  
lan wake-up pin assignments 32  
lan wakeup 32  
A
ACPI 22  
address map  
memory pin assignments 26  
monitor 25  
parallel port 34  
parallel port pin assignments 34  
PCI 27  
PCI pin assignments 27  
power supply 20, 31  
power supply pin assignments 31  
RIMM 26  
serial pin assignments 34  
serial ports 34  
USB 33  
USB port pin assignments 33  
Wake on LAN 32  
DMA 38  
I/O 36  
system memory 36  
advanced configuration and power interface 22  
advanced power management 22  
APM (advanced power management) 22  
audio  
adapter  
controller  
device drivers  
subsystem  
9
9
9
9
audio connector pin assignments 33  
controller  
B
audio  
9
beep codes 41  
BIOS 21  
diskette drive 10  
hard disk drive 24  
I/O 10  
keyboard/mouse 11  
parallel 10  
BIOS data areas 36  
bus  
IDE  
low pin count (LPC)  
LPC  
6
7
serial 10  
7
PCI 6, 12  
universal serial bus  
6
D
diagnostic program 22  
digital video interface (DVI) 25  
diskette drive  
C
cache, L2  
4
controller 10  
chip set 4, 10  
clock, real-time 12  
CMOS RAM 12  
compatibility  
DMA (direct memory access) channel assignments 40  
E
hardware 23  
software 24  
EEPROM 12  
electrically erasable, programmable, read-only memory  
(EEPROM) 12  
Enhanced Diagnostics 22  
environment, operating 16  
error codes, POST 41  
Ethernet port 11  
component maximum current 19  
configuration/setup utility program 22  
connector  
Alert on LAN 32  
alert on lan pin assignments 32  
cable 14  
connector panel 15  
diskette drive 31  
diskette drive pin assignments 31  
IDE 30  
F
fault, overvoltage 20  
features  
IDE pin assignments 30  
ISA bus 29  
ISA pin assignments 29  
keyboard/mouse pin assignments 33  
keyboard/mouse ports 33  
general  
microprocessor  
network support  
system board  
video  
1
4
2
4
7
44  
Copyright IBM Corp. September 1999  
 
Index  
features (continued)  
memory (continued)  
Wake on LAN  
Wake on Ring  
flash EEPROM 12  
flash update 22  
2
3
Rambus dynamic random access memory  
(RDRAM)  
Rambus inline memory module (RIMM)  
connectors  
RDRAM (Rambus dynamic random access  
memory)  
system memory map 36  
video  
5
5
frequency, input power 18  
5
H
9
hard disk drive  
messages, POST error 41  
microprocessor  
compatibility 24  
controller 24  
hardware compatibility 23  
hardware interrupts 23  
features  
modes, power management 22  
monitor support  
4
9
monitor, DVI pin assignments 25  
monitor, SVGA pin assignments 25  
I
I/O  
address map 36  
controller 10  
diskette drive 10  
features 14  
N
network  
connection 11  
support  
2
keyboard 10, 11  
mouse 10, 11  
parallel port 10  
parallel port assignments 10  
serial port 10  
noise level 16, 17  
O
ordering publications vii  
outputs, power supply 19  
overvoltage fault 20  
IDE interface  
6
information, related vii  
input power  
frequency 18  
requirements 18  
voltage 18  
P
parallel port 10  
parallel port assignments 10  
PCI  
interrupt request assignments 40  
bus  
6
J
configuration space map 39  
connectors 12  
jumper  
configuration 14  
locations (system board) 12  
Pentium III microprocessor with MMX technology  
physical layout 12  
Plug and Play 21  
polling mechanism 24  
port  
4
L
L2 cache  
4
ethernet 11  
LED connectors 32  
level-sensitive interrupts 23  
load currents 19  
keyboard/mouse 11  
parallel 10  
serial 10  
POST 21, 36  
POST error codes 41  
power  
M
machine-sensitive programs 24  
consumption 22  
description 18  
for components 19  
input 18  
load currents 19  
management modes 22  
main memory  
memory  
5
configuration tables  
error in 36  
map, system 36  
RAM 36  
5
Index 45  
 
Index  
power (continued)  
output 18  
universal serial bus (continued)  
technology  
6
output protection 20  
outputs 19  
protection, power supply 20  
publications, related vii  
V
video  
accelerated graphics port (AGP)  
7
adapter  
features  
memory  
modes  
monitor support  
resources  
subsystem  
7
7
9
R
RAM (random access memory) 36  
Rambus dynamic random access memory (RDRAM)  
random access memory (RAM) 36  
RDRAM (Rambus dynamic random access memory)  
real-time clock 12  
5
5
8
9
8
7
references 43  
related information vii  
reserved  
voltage, input power 18  
voltage, output power 18  
areas vii  
RFID 32  
radio frequency identification 32  
Riser card layout 13  
W
Wake on LAN  
cable requirements 17  
Wake on LAN support  
Wake on Ring  
2
S
Wake on Ring  
3
serial port 10  
serial port assignments 10  
short circuit 20  
software  
compatibility 24  
interrupts 24  
machine-sensitive programs 24  
specifications 16, 17  
desktop 16  
mechanical 16  
tower 17  
system  
compatibility 23  
memory  
5
memory maps 36  
software 21  
specifications 16  
system board  
features  
4
layout 13  
T
tamper switch 32  
tamper switch assignments 32  
terminology vii  
token ring port 11  
U
universal serial bus  
connectors 33  
port  
6
46 Technical Information Manual  
 

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